This invention relates to semiconductor device fabrication processes. More specifically, the invention relates to plasma-based chemical vapor deposition and etch processes for forming dielectric layers, particularly in high aspect ratio, narrow width recessed features.
It is often necessary in semiconductor processing to fill high aspect ratio gaps with insulating material. This is the case for shallow trench isolation, inter-metal dielectric layers, passivation layers, etc. As device geometries shrink and thermal budgets are reduced, void-free filling of narrow width, high aspect ratio (AR) spaces (e.g., AR>3:1) becomes increasingly difficult due to limitations of existing deposition processes.
The deposition of silicon dioxide (SiO2) assisted by high-density plasma chemical vapor deposition (HDP CVD)—a directional (bottom-up) CVD process—has become the preferred method for high aspect ratio gap fill. The method deposits more material at the bottom of a high aspect ratio structure than on its sidewalls. It accomplishes this by directing charged dielectric precursor species downward, to the bottom of the gap. Thus, HDP CVD is not an entirely diffusion-based (isotropic) process.
An etch-enhanced (deposition-etch-deposition) gap fill technique which involves a sequence of deposition, etch and deposition steps using an HDP reactor has been developed to maintain the opening at the top of the gap wide enough for a subsequent deposition(s) to completely fill the gap. Such processes are described, for example, in U.S. Pat. Nos. 6,335,261 and 6,030,881, the disclosures of which are incorporated herein by reference for all purposes. A typical 3-step etch-enhanced process can be described as follows: First step—Deposition 1: a partial deposition of SiO2 thin film is conducted to obtain maximum bottom-up gap fill with the gap remaining unclosed; second step—Etch: in-situ etch back is carried out to remove depositions on the top and sidewall of the trench lines and keep the mouth of the gap open enough for the next deposition step with minimum bottom-up deposition loss; and, third step—Deposition 2: deposition of SiO2 film is carried out to further fill the partially filled gap to completion. In some cases it may be necessary to conduct additional etch and deposition steps to completely fill the gap.
The etch component of these etch-enhanced gap fill processes typically uses a fluorine-based etchant, such as NF3, CF4 or C2F6, etc., to achieve a fast etch rate. However, the application of those etchants may contaminate the dielectric (e.g., STI) film with foreign atoms, e.g., C, N and F, causing issues in the subsequent integration processes and device degradation.
Therefore, an etch-enhanced gap fill process that avoided the use of etchants which tend to contaminate the deposited dielectric film would be desirable.